An underappreciated step in the chip manufacturing process is becoming the next bottleneck for artificial intelligence.
Any microchip used to power artificial intelligence must be built into hardware that can interact with the outside world. But currently, almost all of this chip manufacturing process, known as advanced packaging, is done in Asia, where production capacity is lacking.
Now, the center stage is the Taiwan Semiconductor Manufacturing Co., Ltd. Two new Arizona factories and Elon Musk Tap prepare to break ground intel for his ambitious custom chip plans.
“If people aren’t aggressively investing in capital to prepare for the surge in fab production that’s going to occur over the next few years, bottlenecks could quickly emerge,” said John Verwey of Georgetown University’s Center for Security and Emerging Technologies.
Paul Rousseau, head of TSMC’s North American packaging solutions, told CNBC in a rare interview that the number is “growing very significantly.”
The most advanced method in use today is called chip-on-wafer-on-substrate (CoWoS), which Rousseau says is growing at an impressive average annual growth rate of 80%.
AI giant Nvidia TSMC has reserved the majority of the state-of-the-art capacity available at TSMC, a volume leader in the packaging space.
But Intel is technologically on par with the Taiwanese giant.
The U.S. chipmaker has struggled to solidify major external customers for its chip manufacturing business, but its packaging customers include companies such as: Amazon and Cisco.
On Tuesday, Musk also announced that SpaceX, xAI, and tesla At his ambitious TerraFab factory planned for Texas.
Intel does most of its final packaging in Vietnam, Malaysia, and China. Some of Intel’s cutting-edge packaging takes place at its U.S. facilities in New Mexico, Oregon, and its facility in Chandler, Arizona, which CNBC toured in November.
This process is gaining traction as AI drives the density, performance, and efficiency needs of chipmakers as they race to develop the best hardware for inference workloads. As transistor density approaches physical limits, new ways to package silicon will help.
“This is actually a natural extension of Moore’s law into three dimensions,” Rousseau said.
For decades, individual chips, known as dies, have been extracted from single wafers and packaged into systems that connect to devices such as computers, robots, cars, and cell phones. As chip complexity has exploded in recent years due to the advent of AI, more advanced packaging methods have become popular.
Multiple dies, such as logic chips and high-bandwidth memory, are now packaged into one large chip, such as a graphics processing unit (GPU). Advanced packaging is used to connect all these dies so that they can communicate with each other and with the broader system.
“Five or six years ago, nobody was doing this,” said Patrick Moorhead, a chip analyst at Moor Insights & Strategy, adding that packaging was an “afterthought” job that companies assigned to junior engineers.
“Now we clearly see that it’s just as important as the mold itself,” he says.
TSMC CoWoS Chip: A sample of a microchip packaged using CoWoS at TSMC’s offices in San Jose, California, published on CNBC on February 20, 2026.
CNBC
bottleneck
Nvidia has reserved most of TSMC’s key CoWoS technology, and with so much capacity reserved, TSMC is reportedly outsourcing some steps to third-party companies like ASE and Amkor that specialize in simpler parts of the process.
ASE, the world’s largest outsourced semiconductor assembly and test company, expects advanced packaging sales to double in 2026. ASE is building a major new facility in Taiwan, and its subsidiary SPIL also held a grand opening for another new packaging location last year, with NVIDIA CEO Jensen Huang in attendance.
In addition to building two packaging facilities in Arizona, TSMC is also expanding with two new packaging facilities in Taiwan.
TSMC currently ships 100% of its chips to Taiwan for packaging, including chips made at its state-of-the-art chip manufacturing facility in Phoenix, Arizona. TSMC did not disclose the expected completion schedule for the U.S. packaging site.
“If we had that capability right next to our Arizona factory, our customers would be very happy,” Jan Vardaman, a leading packaging researcher at TechSearch International, told CNBC.
This is because it eliminates the need to shuttle goods between Asia and the US, shortening delivery times, he added.
intel already has some packaging done near its new advanced 18A chip manufacturing facility in Arizona.
The U.S. chipmaker has not yet secured a major external customer to make chips in its 18A fab, but Mark Gardner, head of foundry services, told CNBC that the company has packaging customers including Amazon and Cisco starting in 2022.
Nvidia is also looking to package Intel as part of its $5 billion investment in the chipmaker, which comes just weeks after the U.S. government invested $8.9 billion in 2025.
“Semiconductor companies want to demonstrate to the U.S. government that they intend to do business with Intel, and a lower-risk way to do business with Intel is through packaging,” Moorhead said.
Asked if Intel could find major chip manufacturing customers through advanced packaging backdoors, Gardner said “that’s a possibility” for some customers.
“There are benefits to having everything in one place,” he said.
Mr. Musk could get early entry into both Intel’s chip manufacturing and packaging.
Intel LinkedIn in a Tuesday post said the company’s “ability to design, manufacture and package ultra-high performance chips at scale” will help Musk’s Terafab achieve its ambition to produce 1 terawatt of AI-powered computing per year.
Shripad Gokhale, an Intel advanced packaging engineer, shows CNBC’s Katie Tarasov Xeon server chips inside Intel’s advanced packaging facility in Chandler, Arizona, on November 17, 2025.
CNBC
Evolution from 2D to 3D
Many chips, such as central processing units, are made with 2D packaging. More complex chips like GPUs require something extra, and this is the realm of TSMC’s CoWoS, a form of 2.5D packaging.
In these chips, an additional layer of dense wiring called an interposer adds tighter interconnects, allowing high-bandwidth memory to be mounted directly around the chip, effectively eliminating what is known as a memory wall.
“You can’t have enough memory on a compute chip to fully utilize it, so with CoWoS we can bring HBM memory right next to the compute in a very efficient way,” said TSMC’s Rousseau.
TSMC developed 2.5D technology in 2012 and has gone through several iterations since then. According to TSMC, Nvidia’s Blackwell GPUs are the first products made with the latest generation of CoWoS-L.
It’s this latest capacity that has everyone worried, as Nvidia has reportedly reserved most of it.
Intel’s cutting-edge packaging technology is called Embedded Multi-Die Interconnect Bridge (EMIB). This works similarly to the process used by Taiwan Semi, but uses a silicon bridge instead of an interposer.
Intel’s Gardner said there are “cost advantages” in “embedding these very small pieces of silicon where you need them.”
All players are also working on what’s coming next: 3D packaging.
Intel calls its method Foveros Direct, while TSMC’s method is called System on Integrated Chips (SoIC).
“Instead of putting the chips side by side, we put one chip on top of the other,” Rousseau explained, adding, “You get a whole other level of performance improvement because you can actually act as if it were one chip.”
Rousseau said it will be several years before TSMC sees packaged products with SoICs.
On the other hand, Samsung, SK Hynix, micron has its own advanced packaging factory and uses 3D packaging to stack die into high-bandwidth memory.
As they rush to ship chips, memory and logic chip makers are also considering a new method called hybrid bonding to replace bumps with copper pads to increase the number of chips that can fit in a stack.
“Instead of a bump, you can have a near-distance pad-to-pad connection, which improves power performance,” Vardaman explained. “It also improves electrical performance because the shortest path is the best path.”
Watch: How advanced packaging is advancing AI chips in 3D
